Semiconductor devices including support pattern and methods of fabricating the same

ABSTRACT

Disclosed are semiconductor devices including support patterns and methods of fabricating the same. The semiconductor devices may include a plurality of vertical structures on a substrate and a support pattern that contacts sidewalls of the plurality of vertical structures. The support pattern may include a plurality of support holes extending through the support pattern. The plurality of support holes may include a first support hole and a second support hole that are spaced apart from each other, and the first support hole may have a shape or size different from a shape or size of the second support hole.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. nonprovisional application is a continuation of U.S. patentapplication Ser. No. 16/860,136, filed on Apr. 28, 2020, which claimspriority under 35 U.S.C § 119 to Korean Patent Application No.10-2019-0096895, filed on Aug. 8, 2019, in the Korean IntellectualProperty Office, and the entire contents of each above-identifiedapplication are hereby incorporated by reference.

BACKGROUND

The present inventive concepts relate to a semiconductor deviceincluding a support pattern and a method of fabricating the same.

Semiconductor devices are beneficial in the electronics industry becauseof their small size, multi-functionality, and/or low fabrication cost.Semiconductor devices are being highly integrated with the remarkabledevelopment of the electronics industry. Line widths of patterns ofsemiconductor devices are being reduced for high integration thereof.Accordingly, new exposure techniques and/or expensive exposuretechniques may be used for forming fine patterns. Various studies haverecently been conducted for new integration techniques.

SUMMARY

Some example embodiments of the present inventive concepts providesemiconductor devices with improved reliability.

Some example embodiments of the present inventive concepts providemethods of fabricating a semiconductor device, which method may reducemanufacturing costs.

According to some example embodiments of the present inventive concepts,semiconductor devices may include a plurality of vertical structures ona substrate and a support pattern that contacts sidewalls of theplurality of vertical structures. The support pattern may include aplurality of support holes extending through the support pattern. Theplurality of support holes may include a first support hole and a secondsupport hole that are spaced apart from each other, and the firstsupport hole may have a shape or size different from a shape or size ofthe second support hole.

According to some example embodiments of the present inventive concepts,semiconductor devices may include a plurality of word lines in asubstrate and parallel to each other and a plurality of first impurityregions and a plurality of second impurity regions in the substrate. Oneof the plurality of first impurity regions and the plurality of secondimpurity regions may be between two adjacent word lines of the pluralityof word lines, and the plurality of first impurity regions and theplurality of second impurity regions may be spaced apart from eachother. The semiconductor devices may also include a plurality of bottomelectrodes on the substrate and electrically connected to the pluralityof first impurity regions, respectively, and a plurality of storage nodecontacts. Each of the plurality of storage node contacts mayelectrically connect a respective one of the plurality of bottomelectrodes to a respective one of the plurality of first impurityregions. The semiconductor devices may further include a plurality oflanding pads, a plurality of bit lines on the substrate and electricallyconnected to the plurality of second impurity regions, respectively, theplurality of bit lines crossing over the plurality of word lines, aplurality of bit-line contacts between a respective one of the pluralityof bit lines and a respective one of the plurality of second impurityregions, and a support pattern in contact with a first portion of asidewall of each of the plurality of bottom electrodes. Each of theplurality of landing pads may be between a respective one of theplurality of storage node contacts and a respective one of the pluralityof bottom electrodes. The support pattern may include a plurality ofsupport holes, and a second portion of the sidewall of each of theplurality of bottom electrodes defines a respective one of the pluralityof support holes. The plurality of support holes may include a firstsupport hole and a second support hole that are spaced apart from eachother. When viewed in plan, the support pattern may include first innersidewalls that define the first support hole and define a circumferenceof a circle. When viewed in plan, the support pattern may include secondinner sidewalls that define the second support hole and define,respectively, sides of a triangle.

According to some example embodiments of the present inventive concepts,methods of fabricating a semiconductor device may include forming a moldlayer and a support layer on a substrate, forming a plurality ofvertical structures extending through the support layer and the moldlayer and including six vertical structures arranged in a honeycombshape when viewed in plan, forming a first mask layer on the supportlayer, forming a plurality of second mask patterns on the first masklayer, each of the plurality of second mask patterns overlappingportions of three neighboring vertical structures and having a circularshape when viewed in plan, and forming a plurality of mask spacers onthe first mask layer. Each of the plurality of mask spacers may be on asidewall of a respective one the plurality of second mask patterns, theplurality of mask spacers may be in contact with each other, and thefirst mask layer may be exposed to a first space between threeneighboring mask spacers. The methods may also include removing theplurality of second mask patterns to form a plurality of second spacesthat expose the first mask layer, forming a first mask pattern, usingthe plurality of mask spacers as an etching mask, by etching the firstmask layer, and forming a plurality of support holes in the supportlayer, using the first mask pattern as an etching mask, by etching thesupport layer. Each of the plurality of mask spacers may have a ringshape when viewed in plan, and a sidewall of each of the plurality ofvertical structures may include a portion defining a respective one ofthe plurality of support holes.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a plan view showing a semiconductor device accordingto some example embodiments of the present inventive concepts.

FIG. 2 illustrates a cross-sectional view taken along lines K-K′ andJ-J′ of FIG. 1.

FIGS. 3A and 3B illustrate plan views showing a semiconductor deviceaccording to some example embodiments of the present inventive concepts.

FIG. 4 illustrates a cross-sectional view taken along lines A-A′ andB-B′ of FIG. 3A or 3B.

FIGS. 5A to 9A illustrate plan views showing a method of fabricating asemiconductor device having the plan view of FIG. 3A.

FIGS. 5B to 9B illustrate cross-sectional views taken along lines A-A′and B-B′ of FIGS. 5A to 9A, respectively.

DETAILED DESCRIPTION

Some example embodiments of the present inventive concepts will now bedescribed in detail with reference to the accompanying drawings to aidin clearly explaining the present inventive concepts.

FIG. 1 illustrates a plan view showing a semiconductor device accordingto some example embodiments of the present inventive concepts. FIG. 2illustrates a cross-sectional view taken along lines K-K′ and J-J′ ofFIG. 1.

Referring to FIGS. 1 and 2, a substrate (e.g., a semiconductorsubstrate) 1 may be provided thereon with device isolation patterns 302defining active sections ACT. Each of the active sections ACT may havean isolated shape. In some embodiments, the active sections ACT may bespaced apart from each other as illustrated in FIG. 1. The substrate 1may be a semiconductor substrate. Each of the active sections ACT mayhave a bar shape elongated along a first direction X1 when viewed inplan. When viewed in plan, the active sections ACT may correspond toportions of the semiconductor substrate 1 that are surrounded by thedevice isolation patterns 302. The semiconductor substrate 1 may includea semiconductor material. The active sections ACT may be arrangedparallel to each other in the first direction X1 such that one of theactive sections ACT may have an end portion adjacent to a centralportion of a neighboring one of the active sections ACT. “When viewed inplan” as used herein may be interchangeable with “when viewed in planview.”

Word lines WL may run across or may traverse the active sections ACT.The word lines WL may be disposed in grooves formed on the deviceisolation patterns 302 and the active sections ACT. The word lines WLmay be parallel to a second direction X2 intersecting the firstdirection X1. In some embodiments, each of the word lines WL may extendlongitudinally in the second direction X2 as illustrated in FIG. 1. Theword lines WL may be formed of a conductive material. A gate dielectriclayer 307 may be disposed between each of the word lines WL and an innersurface of each groove. Although not shown, each of the grooves may havea bottom surface that is relatively deeper in the device isolationpattern 302 and relatively shallower in the active section ACT. The gatedielectric layer 307 may include one or more of thermal oxide, siliconnitride, silicon oxynitride, and/or high-k dielectric. Each of the wordlines WL may have a curved bottom surface. As used herein the term“and/or” includes any and all combinations of one or more of theassociated listed items.

A first doped region 312 a may be disposed in the active section ACTbetween a pair of word lines WL, and a pair of second doped regions 312b may be disposed in opposite edges of each active section ACT. Thefirst and second doped regions 312 a and 312 b may be doped with, forexample, N-type impurities. The first doped region 312 a may correspondto a common drain region, and the second doped regions 312 b maycorrespond to source regions. A transistor may be constituted by each ofthe word lines WL and its adjacent first and second doped regions 312 aand 312 b. Because the word lines WL are disposed in the grooves, eachof the word lines WL may have thereunder a channel region whose lengthbecomes increased within a limited planar area. Accordingly,short-channel effects and the like may be reduced or minimized.

The word lines WL may have their top surfaces lower than those of theactive sections ACT. In some embodiments, the word lines WL may berecessed toward the substrate 1 with respect to the active sections ACT.A word-line capping pattern 310 may be disposed on each of the wordlines WL. The word-line capping patterns 310 may have their linearshapes extending along longitudinal directions of the word lines WL, andmay cover entire top surfaces of the word lines WL. The grooves may havetheir inner spaces not occupied by the word lines WL, and the word-linecapping patterns 310 may fill (e.g., partially fill or completely fill)the unoccupied inner spaces of the grooves. The word-line cappingpatterns 310 may be formed of, for example, a silicon nitride layer.

An interlayer dielectric pattern 305 may be disposed on thesemiconductor substrate 1. The interlayer dielectric pattern 305 may beformed of a single layer or multiple layers including one or more of asilicon oxide layer, a silicon nitride layer, and a silicon oxynitridelayer. The interlayer dielectric pattern 305 may be formed to haveisland shapes spaced apart from each other in a plan view. Theinterlayer dielectric pattern 305 may be formed to simultaneously coverend portions of two adjacent active sections ACT.

Upper portions of the semiconductor substrate 1, the device isolationpattern 302, and the word-line capping pattern 310 may be partiallyrecessed to form a first recess region R1. The first recess region R1may have a sidewall aligned with that of the interlayer dielectricpattern 305.

Bit lines BL may be disposed on the interlayer dielectric pattern 305.The bit lines BL may run across or may traverse the word-line cappingpatterns 310 and the word lines WL. The bit lines BL may be parallel toa third direction X3 intersecting the first and second directions X1 andX2. In some embodiments, each of the bit lines BL may extendlongitudinally in the third direction X3 as illustrated in FIG. 1. Eachof the bit lines BL may include, for example, a bit-line polysiliconpattern 330, a bit-line ohmic pattern 331, and a bit-linemetal-containing pattern 332 that are sequentially stacked. The bit-linepolysilicon pattern 330 may include impurity-doped polysilicon and/orimpurity-undoped polysilicon. The bit-line ohmic pattern 331 may includea metal silicide layer. The bit-line metal-containing pattern 332 mayinclude one or more of metal (e.g., tungsten, titanium, and tantalum)and conductive metal nitride (e.g., titanium nitride, tantalum nitride,and tungsten nitride). A bit-line capping pattern 337 may be disposed oneach of the bit lines BL. The bit-line capping patterns 337 may beformed of a dielectric material, such as a silicon nitride layer.

Bit-line contacts DC may be disposed in the first recess regions R1intersecting the bit lines BL. The bit-line contacts DC may includeimpurity-doped polysilicon and/or impurity-undoped polysilicon. Thebit-line contact DC may have a sidewall in contact with a lateralsurface of the interlayer dielectric pattern 305. When viewed in plan asshown in FIG. 1, the bit-line contact DC may have a concave lateralsurface in contact with the interlayer dielectric pattern 305. Thebit-line contact DC may electrically connect the first doped region 312a to the bit line BL.

The first recess region R1 may have a space not occupied by the bit-linecontact DC, and a lower buried dielectric pattern 341 may occupy thatspace of the first recess region R1. The lower buried dielectric pattern341 may be formed of a single layer or multiple layers including one ormore of a silicon oxide layer, a silicon nitride layer, and a siliconoxynitride layer.

Storage node contacts BC may be disposed between a pair of adjacent bitlines BL. The storage node contacts BC may be spaced apart from eachother. The storage node contacts BC may include impurity-dopedpolysilicon and/or impurity-undoped polysilicon. The storage nodecontacts BC may have their concave top surfaces. Between the bit linesBL, a dielectric pattern (not shown) may be disposed between the storagenode contacts BC.

A bit-line spacer SP may be interposed between the bit line BL and thestorage node contact BC. The bit-line spacer SP may include a firstsub-spacer 321 and a second sub-spacer 325 that are spaced apart fromeach other across a gap region GP. The gap region GP may also be calledan air gap. The first sub-spacer 321 may cover a sidewall of the bitline BL and a sidewall of the bit-line capping pattern 337. The secondsub-spacer 325 may be adjacent to the storage node contact BC. In someembodiments, the first sub-spacer 321 and the second sub-spacer 325 mayinclude the same material. For example, the first sub-spacer 321 and thesecond sub-spacer 325 may include a silicon nitride layer.

The second sub-spacer 325 may have a bottom surface lower than that ofthe first sub-spacer 321. The second sub-spacer 325 may have a top endwhose level is lower than that of a top end of the first sub-spacer 321.The first sub-spacer 321 may extend to cover a sidewall of the bit-linecontact DC and also to cover a sidewall and a bottom surface of thefirst recess region R1. For example, the first sub-spacer 321 may beinterposed between the bit-line contact DC and the lower burieddielectric pattern 341, between the word-line capping pattern 310 andthe lower buried dielectric pattern 341, between the semiconductorsubstrate 1 and the lower buried dielectric pattern 341, and between thedevice isolation pattern 302 and the lower buried dielectric pattern341.

A storage node ohmic layer 309 may be disposed on the storage nodecontact BC. The storage node ohmic layer 309 may include metal silicide.A diffusion stop pattern 311 a may conformally cover the storage nodeohmic layer 309, the first and second sub-spacers 321 and 325, and thebit-line capping pattern 337. The diffusion stop pattern 311 a mayinclude, for example, metal nitride, such as a titanium nitride layerand a tantalum nitride layer. A landing pad 11 may be disposed on thediffusion stop pattern 311 a. The landing pad 11 may be formed ofmaterial containing metal, such as tungsten. The landing pad 11 may havean upper portion that covers a top surface of the bit-line cappingpattern 337 and has a width greater than that of the storage nodecontact BC. A center of the landing pad 11 may shift in the seconddirection X2 away from a center of the storage node contact BC. Aportion of the bit line BL may be vertically overlapped by the landingpad 11. The bit-line capping pattern 337 may have a first upper sidewallthat is overlapped by the landing pad 11 and is covered with a thirdsub-spacer 327. A second recess region R2 may be formed on a secondupper sidewall of the bit-line capping pattern 337. The second uppersidewall of the bit-line capping pattern 337 may be opposite the firstupper sidewall thereof “An element A vertically overlapping an elementB” (or similar language) as used herein means that at least one verticalline intersecting both the elements A and B exists. A vertical directionas used herein refers to a direction that is perpendicular to an uppersurface of the semiconductor substrate 1.

A sum of widths of the first sub-spacer 321 and the third sub-spacer 327on an upper portion of the bit-line spacer SP may be less than a sum ofwidths of the first sub-spacer 321, the gap region GP, and the secondsub-spacer 325 on a lower portion of the bit-line spacer SP. Such aconfiguration may increase a formation margin for the landing pad 11. Asa result, disconnection between the landing pad 11 and the storage nodecontact BC may be reduced or possibly prevented.

A separation dielectric pattern 3 may be disposed on the second recessregion R2. The separation dielectric pattern 3 may define a top end ofthe gap region GP. The separation dielectric pattern 3 may include asilicon nitride layer, a silicon oxide layer, a silicon oxynitridelayer, a silicon carbonitride layer, and/or a porous layer. Theseparation dielectric pattern 3 may have a top surface coplanar withthose of the landing pads 11. The separation dielectric pattern 3 may becovered with an etch stop layer 5 between bottom electrodes 13 whichwill be discussed below. The etch stop layer 5 may include, for example,a dielectric material, such as a silicon nitride layer, a silicon oxidelayer, and/or a silicon oxynitride layer.

Bottom electrodes 13 may be disposed on corresponding landing pads 11.The bottom electrode 13 may include one or more of an impurity-dopedpolysilicon layer, a metal nitride layer such as a titanium nitridelayer, and a metal layer such as a tungsten layer, an aluminum layer,and a copper layer. The bottom electrode 13 may have a circular pillarshape, a hollow cylindrical shape, or a cup shape. A support pattern 9 pmay connect upper sidewalls of neighboring bottom electrodes 13. Thesupport pattern 9 p may include, for example, a dielectric material,such as a silicon nitride layer, a silicon oxide layer, a siliconoxynitride layer, and/or a silicon carbonitride layer (e.g., SiCN). Thesupport pattern 9 p will be further discussed in detail below. “Anelement having a circular pillar shape” as used herein may refer to anelement having a cylindrical shape that includes a circular bottomsurface and a vertical portion protruding from the circular bottomsurface in a vertical direction. The vertical portion of the element mayor may not have a sidewall perpendicular to the circular bottom surface.The vertical portion of the element may have a curved sidewall (e.g., aconcave sidewall or a convex sidewall). The element having a cylindricalshape may have a uniform width along its height direction or may have anon-uniform width along its height direction. “An element having acircular pillar shape” may be referred to as “a vertical structure”.

A dielectric layer 31 may cover surfaces of the bottom electrodes 13 anda surface of the support pattern 9 p. The dielectric layer 31 may beformed of, for example, a metal oxide layer, such as an aluminum oxidelayer, whose dielectric constant is greater than that of a silicon oxidelayer.

The dielectric layer 31 may be covered with a top electrode 33. The topelectrode 33 may include one or more of an impurity-doped polysiliconlayer, an impurity-doped silicon germanium layer, a metal nitride layersuch as a titanium nitride layer, and a metal layer such as a tungstenlayer, an aluminum layer, and a copper layer. A capacitor CAP may beconstituted by the bottom electrode 13, the dielectric layer 31, and thetop electrode 33.

FIGS. 3A and 3B illustrate plan views showing a semiconductor deviceaccording to some example embodiments of the present inventive concepts.FIG. 4 illustrates a cross-sectional view taken along lines A-A′ andB-B′ of FIG. 3A or 3B.

Referring to FIGS. 3A, 3B, and 4, there may be disposed a semiconductorsubstrate 1, a separation dielectric pattern 3, a landing pad 11, anetch stop layer 5, bottom electrodes 13, a support pattern 9 p, adielectric layer 31, a top electrode 33, and an upper interlayerdielectric layer 35. A structure below the bottom electrodes 13 may beidentical or similar to that discussed above with reference to FIGS. 1and 2. The support pattern 9 p may be in contact with sidewalls of allof the bottom electrodes 13. The support pattern 9 p may include supportholes H1, H2, and H3. In some embodiments, each of the holes H1, H2, andH3 of the support pattern 9 p may extend through the support pattern 9 pin the vertical direction.

When viewed in plan as shown in FIGS. 3A and 3B, the bottom electrodes13 may be arranged in a honeycomb shape. For example, a hexagon may beobtained when connecting centers of six bottom electrodes 13 that areadjacent to (or substantially equally spaced from) and surround one(i.e., a single) bottom electrode 13. Each of the support holes H1, H2,and H3 may simultaneously expose sidewalls of three bottom electrodes 13that are adjacent to each other. In some embodiments, portions ofsidewalls of three bottom electrodes 13 that are adjacent to each othermay define one of the support holes H1, H2, and H3, and a layer (e.g.,the dielectric layer 31) in the one of the support holes H1, H2, and H3may contact those portions of the sidewalls of the three bottomelectrodes 13. The support holes H1, H2, and H3 may include firstsupport holes H1, second support holes H2, and third support holes H3.The bottom electrodes 13 may include first bottom electrodes 13 a,second bottom electrodes 13 b, and third bottom electrodes 13 c.

For example, referring to FIG. 3A, when viewed in plan, a first triangleT1 may be obtained when connecting inner sidewalls of the first supporthole H1. Those inner sidewalls of the first support hole H1 are definedby the support pattern 9 p and may be straight. The first support holeH1 may expose sidewalls of three first bottom electrodes 13 a that areadjacent to each other. Three first bottom electrodes 13 a that areadjacent to each other may include respective sidewalls, and portions ofthese sidewalls of the three first bottom electrodes 13 a may define asingle first support hole H1. A layer (e.g., the dielectric layer 31) inthe single first support hole H1 may contact those portions of thesidewalls of the three first bottom electrodes 13 a. The first bottomelectrodes 13 a may be disposed on corresponding vertices of the firsttriangle T1. When viewed in plan, a second triangle T2 may be obtainedwhen connecting inner sidewalls of the second support hole H2. Thoseinner sidewalls of the second support hole H2 are defined by the supportpattern 9 p and may be straight. The second support hole H2 may exposesidewalls of three second bottom electrodes 13 b that are adjacent toeach other. The second bottom electrodes 13 b may be disposed oncorresponding centers of edges of the second triangle T2. Three secondbottom electrodes 13 b that are adjacent to each other may includerespective sidewalls, and portions of these sidewalls of the threesecond bottom electrodes 13 b may define a single second support holeH2. A layer (e.g., the dielectric layer 31) in the single second supporthole H2 may contact those portions of the sidewalls of those threesecond bottom electrodes 13 b. A circle C may be obtained whenconnecting inner sidewalls of the third support hole H3. Those innersidewalls of the third support hole H3 are defined by the supportpattern 9 p and may be curved. In some embodiments, each of those innersidewalls of the third support hole H3 may be a portion of acircumference of the circle C in a plan view as illustrated in FIG. 3A.The third support hole H3 may expose sidewalls of three third bottomelectrodes 13 c that are adjacent to each other. The first triangle T1and the second triangle T2 may have the same size (e.g., width). In someembodiments, sides of the first triangle T1 may have a first lengthequal to a second length of sides of the second triangle T2 asillustrated in FIG. 3A. The size (e.g., width) of the first and secondtriangles T1 and T2 may be different from a size (e.g., diameter) of thecircle C. A hexagon may be obtained when connecting centers of the firstand second support holes H1 and H2 that form six triangles T1 and T2arranged around one third support hole H3 that forms the circle C. Forexample, three first support holes H1 and three second support holes H2may be arranged around one third support hole H3 shaping the circle C.In some embodiments, three first support holes H1 and three secondsupport holes H2 may be arranged in an alternating sequence around asingle third support hole H3, and centers of those three first supportholes H1 and three second support holes H2 may overlap vertices of ahexagon HX, respectively, as illustrated in FIG. 3A.

In some embodiments, the support pattern 9 p may include three firstinner sidewalls that define the first support hole H1 and define,respectively, sides of the first triangle T1 as illustrated in FIG. 3A.In some embodiments, the support pattern 9 p may include six secondinner sidewalls that define the second support hole H2, and pairs of thesecond inner sidewalls define, respectively, sides of the secondtriangle T2 as illustrated in FIG. 3A. In some embodiments, the supportpattern 9 p may include three third inner sidewalls that define thethird support hole H3 and define the circumference of the circle C asillustrated in FIG. 3A. “A sidewall defines a side of a triangle” (orsimilar language) as used herein means that the sidewall defines aportion of the side of the triangle but does not necessarily mean thatthe sidewall defines the entire side of the triangle. “Sidewalls definea circumference of a circle” (or similar language) as used herein meansthat the sidewalls define portions of the circumference of the circlebut does not necessarily mean that the sidewalls define the entirecircumference of the circle.

In some embodiments, the first support hole H1, the third support holeH3, and the second support hole H2 may be immediately adjacent to eachother and may be sequentially arranged along a direction that isdifferent from the second direction X2 and the third direction X3 asillustrated in FIG. 3A. When the first support hole H1, the thirdsupport hole H3, the second support hole H2 are immediately adjacent toeach other, there is no intervening support hole between the firstsupport hole H1 and the third support hole H3 and between the thirdsupport hole H3 and the second support hole H2.

In some embodiments, referring to FIG. 3B, when viewed in plan, a firstcircle C1 may be obtained when connecting inner sidewalls of any of thefirst and second support holes H1 and H2. Those inner sidewalls of oneof the first and second support holes H1 and H2 are defined by thesupport pattern 9 p and may be curved. In some embodiments, those innersidewalls of one of the first and second support holes H1 and H2 maydefine a circumference of the first circle C1 in plan as illustrated inFIG. 3B. A second circle C2 may be obtained when connecting innersidewalls of the third support hole H3. Those inner sidewalls of thirdsupport hole H3 are defined by the support pattern 9 p and may becurved. In some embodiments, those inner sidewalls of third support holeH3 may define a circumference of the second circle C2 in plan asillustrated in FIG. 3B. The first circle C1 may have a first diameterD1. The second circle C2 may have a second diameter D2. The firstdiameter D1 may be different from the second diameter D2. For example,the first diameter D1 may be greater than the second diameter D2.

In some embodiments, the support pattern 9 p may include inner sidewallsthat define a single support hole (e.g., the first support hole H1 orthe second support hole H2), and these inner sidewalls of the supportpattern 9 p may define the circumference of the first circle C1 asillustrated in FIG. 3B. In some embodiments, the support pattern 9 p mayinclude three inner sidewalls that define a single third support holeH3, and these inner sidewalls of the support pattern 9 p may define thecircumference of the second circle C2 as illustrated in FIG. 3B.

The support pattern 9 p may have a top surface coplanar with those ofthe bottom electrodes 13, as shown in FIG. 4, or lower than those of thebottom electrodes 13, as shown in FIG. 2. The support pattern 9 p mayhave a single-layered structure as illustrated in FIG. 4 or 2, or amulti-layered structure having a plurality of layers at differentlevels.

FIGS. 5A to 9A illustrate plan views showing a method of fabricating asemiconductor device having the plan view of FIG. 3A. FIGS. 5B to 9Billustrate cross-sectional views taken along line A-A′ and B-B′ of FIGS.5A to 9A, respectively.

Referring to FIGS. 5A and 5B, landing pads 11 and a separationdielectric pattern 3 may be formed on a semiconductor substrate 1. Anetch stop layer 5, a mold layer 7, and a support layer 9 may besequentially formed on the landing pads 11 and the separation dielectricpattern 3. The mold layer 7 may be formed of a material having an etchselectivity with respect to both the etch stop layer 5 and the supportlayer 9. For example, the mold layer 7 may be formed of a silicon oxidelayer. The support layer 9, the mold layer 7, and the etch stop layer 5may be sequentially etched to form bottom-electrode holes 12 that exposethe landing pads 11. A conductive layer may be formed to fill (e.g.,partially fill or completely fill) the bottom-electrode holes 12, and anetch-back and/or chemical mechanical polishing (CMP) process may beperformed to form bottom electrodes 13 in the bottom-electrode holes 12.The bottom electrodes 13 may be arranged in a honeycomb shape HB. Forexample, a hexagon may be obtained when connecting centers of six bottomelectrodes 13 that are adjacent to (or substantially equally spacedfrom) and surround one bottom electrode 13. The bottom electrodes 13 mayinclude first bottom electrodes 13 a, second bottom electrodes 13 b, andthird bottom electrodes 13 c.

Referring to FIGS. 6A and 6B, a first mask layer 15 may be formed on thesupport layer 9. The first mask layer 15 may include a material, such asa polysilicon layer, a silicon carbonitride layer, and/or a siliconoxynitride layer, having an etch selectivity with respect to the supportlayer 9. Second mask patterns 17 may be formed on the first mask layer15. The second mask patterns 17 may be spaced apart from each other andmay each have a circular shape when viewed in plan. The second maskpatterns 17 may be formed of a material having an etch selectivity withrespect to the first mask layer 15, which material may include, forexample, a photoresist pattern, a spin-on-hardmask (SOH) layer, aspin-on-carbon (SOC) layer, and/or an amorphous carbon layer (ACL). Onesecond mask pattern 17 may be disposed to simultaneously overlap threethird bottom electrodes 13 c that are adjacent to each other. At leastone bottom electrode 13 may be disposed between the second mask patterns17 and not overlapped by the second mask patterns 17. The total numberof the second mask patterns 17 may be less than that of support holesH1, H2, and H3 which will be formed later. An interval or a shortestdistance between the second mask patterns 17 may be greater than thatbetween support holes H1, H2, and H3 (e.g., a shortest distance betweenthe first hole H1 and the second hole H2 closest to the first hole H1)which will be formed later. The second mask patterns 17 may be formed byemploying an immersion photolithography apparatus.

A third mask layer may be conformally formed on the first mask layer 15,and then anisotropically etched to form mask spacers 19 that coversidewalls of the second mask patterns 17. The mask spacers 19 may beformed of a material, such as a silicon oxide layer, having an etchselectivity with respect to both the first mask layer 15 and the secondmask patterns 17. The mask spacers 19 may each have a ring shape whenviewed in plan. The mask spacers 19 may be in contact with each other.The mask spacers 19 may have their edges that overlap the first bottomelectrodes 13 a. The second bottom electrodes 13 b may be spaced apartfrom both the second mask patterns 17 and the edges of the mask spacers19. In some embodiments, the second bottom electrodes 13 b may be spacedapart from both the second mask patterns 17 and the edges of the maskspacers 19 in plan as illustrated in FIG. 6A.

A first space S1 and a second space S2 may be formed between the maskspacers 19 and may expose the first mask layer 15. For example, thefirst space S1 may be formed between three mask spacers 19 that areadjacent to each other. The second space S2 spaced apart from the firstspace S1 may be formed between other three mask spacers 19 that areadjacent to each other. When viewed in plan, the first space S1 and thesecond space S2 may each have a triangular-like shape when viewed inplan. The first bottom electrodes 13 a may be overlapped by an edge ofthe first space S1. The second bottom electrodes 13 b may be adjacent toan edge of the second space S2.

Referring to FIGS. 7A and 7B, an isotropic etching process may beperformed such that the second mask patterns 17 may be selectivelyremoved to form a third space S3 that is surrounded by the mask spacer19 and exposes the first mask layer 15. The third space S3 may expose aninner sidewall of the mask spacer 19. The third space S3 may have acircular shape when viewed in plan. The third space S3 may have an edgethat overlaps three third bottom electrodes 13 c that are adjacent toeach other.

Referring to FIGS. 7A, 7B, 8A, and 8B, the mask spacers 19 may be usedas an etching mask to etch the first mask layer 15 to form a first maskpattern 15 p. In this case, the first space S1 and the second space S2may be transferred onto the first mask pattern 15 p to form a triangularfirst opening OP1 and a triangular second opening OP2. In addition, thethird space S3 may be transferred onto the first mask pattern 15 p toform a circular third opening OP3. The first opening OP1 may exposeportions of top surfaces of three first bottom electrodes 13 a that areadjacent to each other and also expose a top surface of the supportlayer 9 between the first bottom electrodes 13 a. The second opening OP2may expose portions of top surfaces of three second bottom electrodes 13b that are adjacent to each other and also expose a top surface of thesupport layer 9 between the second bottom electrodes 13 b. The thirdopening OP3 may expose portions of top surfaces of three third bottomelectrodes 13 c that are adjacent to each other and also expose a topsurface of the support layer 9 between the third bottom electrodes 13 c.

Referring to FIGS. 8A, 8B, 9A, and 9B, the first mask pattern 15 p maybe used as an etching mask to etch the support layer 9 to form a supportpattern 9 p. In this case, the first opening OP1 and the second openingOP2 may be transferred onto the support pattern 9 p to form a triangularfirst support hole H1 and a triangular second support hole H2. Inaddition, the third opening OP3 may be transferred onto the supportpattern 9 p to form a circular third support hole H3. The first supporthole H1 may expose portions of sidewalls of three first bottomelectrodes 13 a that are adjacent to each other and also expose a topsurface of the mold layer 7 between the first bottom electrodes 13 a.The second support hole H2 may expose portions of sidewalls of threesecond bottom electrodes 13 b that are adjacent to each other and alsoexpose a top surface of the mold layer 7 between the second bottomelectrodes 13 b. The third support hole H3 may expose portions ofsidewalls of three third bottom electrodes 13 c that are adjacent toeach other and also expose a top surface of the mold layer 7 between thethird bottom electrodes 13 c.

Subsequently, an isotropic etching process may be performed to removethe mold layer 7 through the support holes H1, H2, and H3, therebyexposing surfaces of the support pattern 9 p, the bottom electrodes 13,and the etch stop layer 5. In this case, the support pattern 9 p mayreduce or possibly prevent collapse of the bottom electrodes 13. Adielectric layer 31 and a top electrode 33 may be sequentially formed.

In the present inventive concepts, the following process options may beselected to control sizes and shapes of the first, second, and thirdsupport holes H1, H2, and H3.

An increase in isotropy or anisotropy of an etching gas may controlsizes and shapes of the first, second, and third support holes H1, H2,and H3.

For example, when the first mask pattern 15 p is formed, or when thesupport pattern 9 p is formed, an increase in directionality of anetching gas (i.e., etchant) may allow the first, second, and thirdsupport holes H1, H2, and H3 to have their shapes that are identicallytransferred from initial shapes of the first, second, and third spacesS1, S2, and S3. In this case, the first and second support holes H1 andH2 may become triangular shaped.

When the first mask pattern 15 p or the support pattern 9 p is formed,an increase in isotropy of an etching gas (i.e., etchant) may form thefirst and second support holes H1 and H2 into a near-circular shape asshown in FIG. 3B. In this case, depending on the degree of etching ofthe first mask pattern 15 p or the support pattern 9 p, the first andsecond support holes H1 and H2 may be formed to have their sizesdifferent from that of the third support hole H3.

In some embodiments, to increase planar sizes (e.g., widths) of thesupport holes H1, H2, and H3, before the first mask layer 15 is etched,a process may be additionally performed to reduce sizes of the maskspacers 19.

In some embodiments, when the support layer 9 is etched to form thesupport pattern 9 p, an over-etching process may be performed on thesupport layer 9 such that an etchant may collide a top surface of themold layer 7 and then may laterally travel to widen the first, second,and third support holes H1, H2, and H3. In this case, the first andsecond support holes H1 and H2 may be formed into a near-circular shapewhen viewed in plan as shown in FIG. 3B. When no over-etching process isperformed on the support layer 9, the first and second support holes H1and H2 may be formed into a near-triangular shape when viewed in plan asshown in FIG. 3A.

In some embodiments, a thickness of the first mask layer 15 may beadjusted to control sizes and shapes of the first, second, and thirdsupport holes H1, H2, and H3. An increase in thickness of the first masklayer 15 may form the first and second support holes H1 and H2 into anear-circular shape when viewed in plan as shown in FIG. 3B. A reductionin thickness of the first mask layer 15 may form the first and secondsupport holes H1 and H2 into a near-triangular shape when viewed in planas shown in FIG. 3A.

In the present inventive concepts, because an interval or a shortestdistance between the second mask patterns 17 is greater than thatbetween the support holes H1, H2, and H3 (e.g., a shortest distancebetween the first hole H1 and the second hole H2 closest to the firsthole H1), the second mask patterns 17 may be formed by employing arelatively low-priced immersion photolithography apparatus instead of arelatively high-priced EUV exposure apparatus. As a result,manufacturing costs may be reduced.

Furthermore, the mask spacers 19 may be used to form the support holesH1, H2, and H3 that expose lateral surfaces of all of the bottomelectrodes 13. Therefore, when an etching process is adopted to removethe mold layer 7 through the support holes H1, H2, and H3, the etchingprocess may be performed in such a way that an etchant may have auniform concentration regardless of position, and that the bottomelectrodes 13 may not be over-etched. In addition, when the dielectriclayer 31 and the top electrode 33 are formed, source gases may have auniform concentration regardless of position, and thus the dielectriclayer 31 and the top electrode 33 may each be formed to have a regularthickness (e.g., a uniform thickness) as a whole. As a result, asemiconductor device may be fabricated to have increased reliability.

A semiconductor device according to the present inventive concepts maybe configured such that support holes of a support pattern exposesidewalls of all of bottom electrodes, which may result in animprovement in reliability of the semiconductor device.

Moreover, in a method of fabricating a semiconductor device according tothe present inventive concepts, second mask patterns may be formed byemploying a relatively low-priced immersion photolithography apparatusinstead of a relatively high-priced EUV exposure apparatus, which mayresult in a reduction in manufacturing costs.

Although the present invention has been described in connection withsome example embodiments of the present inventive concepts illustratedin the accompanying drawings, it will be understood by those skilled inthe art that various changes and modifications may be made withoutdeparting from the scope of the present inventive concepts. It will beapparent to those skilled in the art that there are various possiblemodifications and changes to the example embodiments of the presentinventive concepts without departing from the scope of the inventiveconcepts.

What is claimed is:
 1. A semiconductor device comprising: a plurality ofword lines in a substrate and parallel to each other; a plurality offirst impurity regions and a plurality of second impurity regions in thesubstrate, wherein one of the plurality of first impurity regions andthe plurality of second impurity regions is between two adjacent wordlines of the plurality of word lines, and the plurality of firstimpurity regions and the plurality of second impurity regions are spacedapart from each other; a plurality of bottom electrodes on the substrateand electrically connected to the plurality of first impurity regions,respectively; a plurality of storage node contacts, wherein each of theplurality of storage node contacts electrically connects a respectiveone of the plurality of bottom electrodes to a respective one of theplurality of first impurity regions; a plurality of landing pads,wherein each of the plurality of landing pads is between a respectiveone of the plurality of storage node contacts and a respective one ofthe plurality of bottom electrodes; a plurality of bit lines on thesubstrate and electrically connected to the plurality of second impurityregions, respectively, the plurality of bit lines crossing over theplurality of word lines; a plurality of bit-line contacts between arespective one of the plurality of bit lines and a respective one of theplurality of second impurity regions; and a support pattern in contactwith a first portion of a sidewall of each of the plurality of bottomelectrodes, wherein: the support pattern includes a plurality of supportholes, and a second portion of the sidewall of each of the plurality ofbottom electrodes defines a respective one of the plurality of supportholes, the plurality of support holes include a first support hole and asecond support hole that are spaced apart from each other, when viewedin plan, the support pattern comprises first inner sidewalls that definethe first support hole and define a circumference of a circle, and whenviewed in plan, the support pattern comprises second inner sidewallsthat define the second support hole and define, respectively, sides of atriangle.
 2. The semiconductor device of claim 1, wherein the firstsupport hole comprises three first support holes and the second supporthole comprises three second support holes, and the three first supportholes and the three second support holes are spaced apart from eachother and arranged in an alternating sequence around a center of ahexagon, and wherein centers of the three first support holes and thethree second support holes overlap, respectively, vertices of thehexagon.
 3. The semiconductor device of claim 1, wherein the pluralityof bottom electrodes comprise three bottom electrodes that are adjacentto each other, and the three bottom electrodes define the first supporthole of the plurality of support holes.
 4. The semiconductor device ofclaim 1, further comprising bit-line spacers on respective sidewalls ofthe plurality of bit lines, wherein each of the bit-line spacersincludes a first sub-spacer and a second sub-spacer that are spacedapart from each other by a gap region between the first sub-spacer andthe second sub-spacer.
 5. The semiconductor device of claim 1, whereinthe plurality of support holes further include a third support hole, andthe triangle is a first triangle, wherein, when viewed in plan, thesupport pattern comprises third inner sidewalls that define the thirdsupport hole and define, respectively, sides of a second triangle, andwherein, when viewed in plan, the second support hole and the thirdsupport hole have different respective shapes.
 6. The semiconductordevice of claim 5, wherein, when viewed in plan, the first, second, andthird support holes are immediately adjacent to each other and arrangedalong a first direction, and the first support hole is between thesecond support hole and the third support hole.
 7. The semiconductordevice of claim 1, further comprising a plurality of separationdielectric patterns, wherein one of the plurality of separationdielectric patterns is interposed between two adjacent landing pads ofthe plurality of landing pads, and wherein top surfaces of the pluralityof separation dielectric patterns are coplanar with top surfaces of theplurality of landing pads.
 8. A semiconductor device comprising: aplurality of vertical structures on a substrate; and a support patternthat contacts sidewalls of the plurality of vertical structures, whereinthe support pattern comprises a plurality of support holes extendingthrough the support pattern, wherein the plurality of support holescomprise a first support hole and a second support hole that are spacedapart from each other, wherein the first support hole has a shape inplan view of a first triangle in which a first subset of three of theplurality of vertical structures are on respective vertices of the firsttriangle, and wherein the second support hole has a shape in plan viewof a second triangle in which a second subset of three of the pluralityof vertical structures are on respective edges of the second triangle.9. The semiconductor device of claim 8, wherein the plurality of supportholes further comprise a third support hole, and wherein the thirdsupport hole has a shape in plan view of a circle in which a thirdsubset of the plurality of vertical structures are around a perimeter ofthe circle.
 10. The semiconductor device of claim 9, wherein a pluralityof the first support holes and a plurality of the second support holesare arranged in an alternating sequence around the third support hole.11. The semiconductor device of claim 10, wherein the plurality of thefirst support holes and the plurality of the second support holes arearranged in the alternating sequence around a center of a hexagon, andwherein centers of the plurality of the first support holes and theplurality of the second support holes overlap, respectively, vertices ofthe hexagon.
 12. The semiconductor device of claim 11, wherein the thirdsupport hole is at the center of the hexagon.
 13. The semiconductordevice of claim 8, wherein, when viewed in plan view, the supportpattern extends on a vertex of the second triangle of the second supporthole.
 14. The semiconductor device of claim 13, wherein the vertex ofthe second triangle of the second support hole extends between twovertical structures of the second subset of three of the plurality ofvertical structures.